My Pet
My pet dog's name is Jack It plays with me And go with me Its favourite drinks is milk And favourite dish is meat We go the park a…
Browse all Saif-Filmannex's Blog Posts
NON- REALISTIC ENDINGS
A few days back I finished watching shehr-e-zaat and came onto a conclusion that from now on I should watch first and last episode…
verilog programing-2
module Topmodule(clk, rst, out);output [3:0] out; input clk, rst;wire dividedCLK, bufferedCLK;wire [3:0] counterOut;BUFG bg(buffer…
verilog programing-1
module top(clk, rst, out);output [3:0] out; input clk, rst;wire dividedCLK, bufferedCLK;wire [3:0] counterOut;BUFG bg(bufferedCLK,…
verilog programing
module shiftreg(out_put, in, s1, s2, msb_in, lsb_in, clk, clr);output [3:0] out_put; reg [3:0]out_put;input [3:0] in;input s1;inpu…
2X1 Mux using Gate-level Modeling
/*Implement a 2X1 Mux using Gate-level Modeling. Simulate in either ModelSim or Xilinx ISE.*/ module mux2 (out,i0,i1,s); output …
implement a 4x16 Decoder using Fpga
implement a 4x16 Decoder Module module decoder(d,w,x,y,z,);input w,x,y,z;output [15:0]d;//vector haiving 16 number of bitsassign …
Implementation of Binary Multiplier through FPGA
Module Multiplier module multiplier(p,a,b); input [3:0] a; input [3:0] b; output [7:0] p; wire e,f,g,h,i,k,m,n,o,q,v,w; assign {e,…
Asynchronous Up-Down 8-bit Counter
Asynchronous Up-Down 8-bit Counter. Module module up_down_counter(q_out,co,Count,incriment,clk,clr); output [7:0]q_out; output co;…
Implementation of RSA algorithm in C++
The RSA Algorithm 1-Based on the idea that factorization of integers into their prime factors is hard.★ n=p．q, where p and q a…
