AMD to reveal technical details about ‘Carrizo’ APU early next year

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Advanced Micro Devices will reveal all technical details about its next-generation code-named “Carrizo” accelerated processing unit in late February, 2015, at the 2015 IEEE international Solid-State Circuits Conference (ISSCC). Although many things about the chip are already known, AMD managed to create an intrigue by squeezing in 28 per cent more transistors without changing process technology or increasing die size.

Based on unofficial information, AMD “Carrizo” accelerated processing unit packs two dual-core AMD “Excavator” (XV) modules, AMD Radeon graphics based on third iteration graphics core next architecture (GCN 1.2) with eight compute units (512 stream processors in total), an integrated dual-channel DDR3 memory controller, a new special high-performance bus to connect x86 cores to graphics cores and DRAM, additional HSA [heterogeneous system architecture] enhancements, PCI Express 3.0 controller as well as all-new multimedia and input/output engines.

According to AMD’s description of the “Carrizo” silicon it plans to describe at the ISSCC, the chip will be made using 28nm process technology. Surprisingly, the APU will integrate 3.1 billion of transistors, 28 per cent more compared to the current-generation “Kaveri” APU, but maintain rather small die size of 244.62mm2 (Kaveri is 245mm2).

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