Introduction To HDL Based Disigning

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HDL Based Modeling and Designing

  • Goal

This  lab exercise is formulated to familiarize the  students with different  IDE and ISE tools for HDL based designing.

  • Equipment Required:

• A Computer

• Xilinx ISE

       

• ModelSim

     

  • Abstraction:

 Hardware  Description  Language  is  a  language  from  a  class  of  computer  languages  or modeling  languages  for brief description and designing of electronic circuits, and most-commonly, digital logic. It can describe the circuit's operation, its design and tests to verify its operation by means of simulation.  The  most popular HDLs are

  • Verilog  
  • VHDL

 Verilog due to its similarity to C language is easier to understand so has

become most widely used HDL in educational institutions.

                   

                           

  • Design Methods

Two basic types of digital design methodologies:

 a top-down design methodology

and

 a bottom-up design methodology.

In top-down design  methodology, we define the top-level  block and  identify the sub blocks necessary to build the top-level block. We further subdivide the sub-blocks until we come to leaf cells, which are the cells that cannot further be divided .

                      

In  bottom -up design methodology, we first identify the building blocks that are available to us. We build bigger cells, using these building blocks. These cells are then used for high-level blocks until we build the top-level block in the design.

  • A Module:

A module is the basic building block in Verilog. A module can be an element or a collection of low-level design blocks.

In Verilog, a  corresponding keyword , endmodule, must appear at the end of the module definition.

Each module must have a  module_name, which is the identifier for the module, and a  module_terminal_list, which describes the input and output terminals of the module.

module  <module_name>  (<module_parmeter_list>);

<module internals>

endmodule

  • Conventions:

The basic lexical conventions used by Verilog HDL are similar to those in the C programming

 Tokens  can  be  comments,  delimiters,  numbers, strings, identifiers, and  keywords. Verilog HDL is a case-sensitive language. All keywords are in

  • Whitespace

Blank spaces , tabs and newlines comprise the whitespace. Whitespace is ignored by Verilog . Whitespace is not ignored in string.

  • Comments

Comments can be inserted in the code for readability and documentation. There are two ways to write comments. A one-line comment starts with "//". Verilog skips from that point to the end of line. A multiple-line comment starts with "/*" and ends with "*/". Multiple-line comments cannot be inserted. However, one-line comments can be embedded in multiple-line comments.

//  a one-line comment

/*  a multiple line

comment */

  • Operators:

Operators  are of three types:

  unary,  binary, 

and  ternary.

 Unary  operators  preceede the  operand.

Binary operators appear between two operands. Ternary operators have two separate operators that separate three operands.

a = ~ b; b is the operand

a = b && c; a = b ? c : d; 3.3.4 Number Specification

There are two types of number specification in Verilog: sized and unsized.

a) Size numbers

Sized numbers are represented as  size '<base format> <number>.

size  is  written  only  in  decimal  and  specifies  the  number  of  bits  in  the  number.  Legal  base formats are decimal ('a or 'A), hexadecimal ('h or 'H), binary ('b or 'B) and octal ('o o r 'O). The number is specified as consecutive digits from 0, 1, 2, 3, … , a, b, c, d, e, f. Only a subset of these digits is legal for a particular base. Uppercase letters are legal for number specification.

4'b1111

12'habc

16'd255

 b) Unsized numbers

Numbers that are specified without a <base format>  specification are decimal numbers by default.

Numbers  that  are  written  without  a  <size>  specification  have  a  default  number  of  bits  that  is

simulator- and machine-specific (must be at least 32).

2345

6'hc

3'o21

  • String

A string is  sequence of characters that are enclosed by double quote. The restriction on a string is  that  it  must  be  contained  on  a  single  line,  that  is,  without  a  carriage  return.  It  cannot  be  on multiple lines. Strings are treated as a sequence of one-byte ASCII values.

"Hello World"

 

  • Identifiers and Keywords

Keywords  are  special  identifier  reserved  to  define  the  language  construct.  Keywords  are  in lowercase.  Identifiers  are   objects  so that they  can  be  referenced  in  the  design. Identifiers are made up of alphanumeric characters, the underscore , or the dollar sign. Identifiers are case sensitive. Identifiers start with an alphabetic character or an underscore. They cannot start with a digit or a $ sign.

reg value;

input clk;



About the author

MuhammadTayyab

Me from Pakistan and im the student of undergraduate;BS Electronics.

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