2X1 Mux using Gate-level Modeling

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/*Implement a 2X1 Mux using Gate-level Modeling.
Simulate in either ModelSim or Xilinx ISE.*/

 

 

module mux2 (out,i0,i1,s);
output out;
input i0,i1,s;
wire s1;
wire y1,y2;
not(s1,s);
and (y1,i0,s1);
and(y2,i1,s);
or (out, y1,y2);
endmodule

module stimuls;
reg IN0,IN1,S;
wire oupt;
mux2 ha(oupt,IN0,IN1,S);
initial
begin
IN0=0;IN1=0;S=0;
#10 IN0=1;IN1=0;S=0;
#10 IN0=0;IN1=0;S=1;
#10 IN0=0;IN1=1;S=1;


end
endmodule

output

 



About the author

Saif-Filmannex

I am doing Bs Electronics Engineering from International Islamic University

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