module Topmodule(clk, rst, out);
output [3:0] out;
input clk, rst;
wire dividedCLK, bufferedCLK;
wire [3:0] counterOut;
BUFG bg(bufferedCLK, dividedCLK);
ClkDivider CD(dividedCLK, clk, rst);
Counter C1(counterOut, bufferedCLK, rst);
Display8leds D1(out,counterout);
endmodule

 

module ClkDivider(out, clk, rst);
output out;
input clk, rst;
reg out;
reg [27:0] counter;
always @(posedge clk, negedge rst)
begin
if(!rst)
begin out <= 0;counter <= 0;
end
else if (counter == 22'h7F2814)
begin out <= !out; counter <= 0;
end
else
counter<= counter + 1;
end
endmodule

 

module Counter(out, clk, rst);
output [3:0] out;
input clk, rst;
reg [3:0] out;
always @(posedge clk, negedge rst)
begin
if(!rst)
out<=0;
else
out<=out + 1;
end
endmodule

 

module Display8leds(out1,out2, in);
output [3:0]out1;
output [3:0]out2;
input [3:0]in;
reg [3:0]out1;
reg [3:0]out2;
always @ (in)
begin
if(in<=4'b1001)
out1=in;
else if(in>=4'b1001)
begin
out2=out2+1;
out1=in;
end
end
endmodule