/*Implement a 4X2 priority encoder using
behavioral modeling. Simulate in either ModelSim
or Xilinx ISE.
.*/

module encoder ( X,Y,V,D);
output X,Y,V;
reg X,Y,V;
input [3:0]D;
always @ (D)
begin
if(D==4'b0000) {X, Y, V} = 3'bxx0;
else
if(D==4'b1000) {X, Y, V} = 3'b001;
else
if(D==4'b0100) {X, Y, V} = 3'b011;
else
if(D==4'b0010) {X, Y, V} = 3'b101;
else
if(D==4'b1111) {X, Y, V} = 3'b111;
else
$display("invalid signal") ;
end
endmodule
module stimulus;
wire X,Y,V;
reg [3:0]D;
encoder ha(X,Y,V,D);
initial
begin
D=0;
#10 D = 4'b0000;
#10 D = 4'b1000;
#10 D = 4'b0100;
#10 D = 4'b0010;
#10 D = 4'b1111;
#10 $stop;
#10 $finish;
end
endmodule

simulation