Keyboard Interfacing with FPGA

Posted on 03 September 2014 at 05:37

Keyboard Interfacing with FPGA

Top Module

module top_keyboard(out,kbrd_clk,kbrd_data,rst);

input kbrd_clk,kbrd_data,rst;
output [3:0]out;

wire [7:0] data;

deserialize des(.in(kbrd_data),.clk(kbrd_clk),.out(data),.rst(rst));
decoder dec(.out(out),.in(data));

endmodule

Deserialize Module

module deserialize(in,clk,out,ready,rst);

input in,clk,rst;
output [7:0] out;
output ready;

reg start_bit,r0,r1,r2,r3,r4,r5,r6,r7,parity,stop;

reg [3:0]counter;
reg ready;
reg [7:0] out;

always@(negedge clk or negedge rst)
begin
if(!rst)
begin
start_bit <= 0;
r0<= 0;
r1<= 0;
r2<= 0;
r3<= 0;
r4<= 0;
r5<= 0;
r6<= 0;
r7<= 0;
parity<= 0;
stop<= 0;
end
else
begin
stop <= in;
parity <= stop;
r7 <= parity;
r6 <= r7;
r5 <= r6;
r4 <= r5;
r3 <= r4;
r2 <= r3;
r1 <= r2;
r0 <= r1;
//start_bit <= r0;
end
end
always@(negedge clk or negedge rst)
begin
if(!rst)
begin counter <= 0; ready <= 0; end
else if(counter == 4'd10)
begin counter <= 0; ready <= 1; end
else
begin counter <= counter + 1; ready <= 0; end
end

always@(posedge clk)
begin
if(ready)
out <= {r7,r6,r5,r4,r3,r2,r1,r0};
else
out <= out;

end

endmodule

Decoder Module

module decoder(out,in);

output [3:0] out;
input [7:0]in;

reg [3:0] out;
always@(in)
begin
case(in)
8'h16: out <= 4'd1;
8'h1: out <= 4'd2;
8'h26: out <= 4'd3;
8'h25: out <= 4'd4;
8'h2E: out <= 4'd5;
8'h36: out <= 4'd6;
8'h3D: out <= 4'd7;
8'h3E: out <= 4'd8;
8'h46: out <= 4'd9;
8'h45: out <= 4'd0;
default : out<= 4'd0;
endcase
end

endmodule

RTL

Implementation on Virtex 2 Pro Board

NET "kbrd_clk" LOC = "AG2" ;
NET "kbrd_data" LOC = "AG1" ;
NET "out[0]" LOC = "AC4" ;
NET "out[1]" LOC = "AC3" ;
NET "out[2]" LOC = "AA6" ;
NET "out[3]" LOC = "AA5" ;
NET "rst" LOC = "AC11" ;