UART

 

 

• Stands for Universal Asynchronous Receiver-Transmitter
• Asynchronous, no need of common clock between transmitter and receiver
• One of the methods of serial communication
• Transfer byte of data at a time
• Interface between PC and fpga

UART TRANSMITTER

 

 

• Set baud rate of UART transmitter
• :. Baud rate=9600
• Baud count=[crystal frequency/baud rate]-1

UART RECIEVER

 

 

• Baud rate of UART receiver is same as transmitter baud rate.
• Baud count=[ (crystal frequency/ baud ratex16)-]
• Receiver clock is 16 times faster as compared to transmitter clock
• BAUD COUNTER: to set a baud count
• BIT DETECTOR: to check bit status, at 2 out of 3 logic.
• SHIFT REGISTER: to shift bit by bit data
• TRASITION 1_to_0= tells us start of data transmission.
• RX CONTROL: checks the bit status of start bit, data and stop bit.
• RS232 RECIEVER: instantiate all the modules/blocks, It is a top file of receiver

CODE

 

1-MODULE

 

 

module uuart_rtl (input clk,input rst,input load_tx,input [7:0] data_tx,input rx,output reg baud_gen,output reg flag_tx,output reg flag_rx,output reg tx,output reg [7:0] data_rx);
reg[11:0] clock_divider;
reg[7:0] shift_register_tx;
reg[7:0] shift_register_rx;
reg load_rx;
wire start_bit;
assign start_bit=1'b0;
wire stop_bit;
assign stop_bit=1'b1;
reg[3:0] cs_tx,ns_tx;
reg[4:0] cs_rx;
reg [4:0] ns_rx;

 

parameter[3:0]s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7,s8=8,s9=9,s10=10;

parameter[4:0]S0=11,S1=12,S2=13,S3=14,S4=15,S5=16,S6=17,S7=18,S8=19,S9=20,S10=21;
///////////////////////////////**********Baud Rate Generator*************/////////////////////////////////

always@(posedge clk)
begin
if(rst)
clock_divider <= 'd0;
else if (clock_divider == 'd624)
clock_divider <= 'd0;
else
clock_divider <= clock_divider + 1'b1;
end

 

always@(posedge clk)
begin
if(rst)
baud_gen <= 1'b0;
else if (clock_divider == 'd624)
baud_gen <= ~baud_gen;
end

/////////////////////////////////********Shift Register*******//////////////////////////////////////////

 

always@(posedge baud_gen)
begin
if(rst==1)
shift_register_tx<='d0;
else if(load_tx)
shift_register_tx<=data_tx;
end

//////////////////////////////////////*************************////////////////////////////////////////

always@(posedge baud_gen)
begin
if(rst)
cs_tx<='d0;
else
cs_tx<=ns_tx;
end

 

always@(*)
begin
case(cs_tx)
s0:
begin
if(load_tx==1)
begin
ns_tx=s1;
flag_tx=0;
end
else if( load_tx==0) ///////////////////////////idle state///////////////////////////////
begin
ns_tx=s0;
flag_tx=1;
end
end

s1:
begin
tx=start_bit;
ns_tx=s2;
flag_tx=0;
end

//////////////////////////////////////Sending Data/////////////////////////////////////////
s2:
begin
tx=shift_register_tx[0];
ns_tx=s3;
flag_tx=0;
end

s3:
begin
tx=shift_register_tx[1];
ns_tx=s4;
flag_tx=0;
end

s4:
begin
tx=shift_register_tx[2];
ns_tx=s5;
flag_tx=0;
end

s5:
begin
tx=shift_register_tx[3];
ns_tx=s6;
flag_tx=0;
end

s6:
begin
tx=shift_register_tx[4];
ns_tx=s7;
flag_tx=0;
end

s7:
begin
tx=shift_register_tx[5];
ns_tx=s8;
flag_tx=0;
end

s8:
begin
tx=shift_register_tx[6];
ns_tx=s9;
flag_tx=0;
end

s9:
begin
tx=shift_register_tx[7];
ns_tx=s10;
flag_tx=0;
end

s10:
begin
tx=stop_bit;
ns_tx=s0;
flag_tx=0;
end
default:
begin
ns_tx=s0;
flag_tx=1;
tx=1;
end
endcase
end

/////////////////////////////////////////////Receiver/////////////////////////////////////////////////////////////////

 

/*always@(posedge baud_gen or posedge rst)
begin
if(rst==1)
shift_register_rx<='d0;
else if(cs_rx == S1)
shift_register_rx[0]<=rx;
else if(cs_rx == S2)
shift_register_rx[1]<=rx;
else if(cs_rx == S3)
shift_register_rx[2]<=rx;
else if(cs_rx == S4)
shift_register_rx[3]<=rx;
else if(cs_rx == S5)
shift_register_rx[4]<=rx;
else if(cs_rx == S6)
shift_register_rx[5]<=rx;
else if(cs_rx == S7)
shift_register_rx[6]<=rx;
else if(cs_rx == S8)
shift_register_rx[7]<=rx;
end*/

 

always@(posedge baud_gen)
begin
if(rst)
cs_rx<='d11;
else
cs_rx<=ns_rx;
end

/* always@(posedge baud_gen)
begin
if(rx==0)
begin
reciever_enable<=1;
wait(flag_rx);
end
else if(rx==1)
reciever_enable<=0;
end*/


always@(*)
begin
case(cs_rx)
S0:
begin
if(rx==0)
begin
ns_rx=S1;
flag_rx=0;
load_rx=0;
end
else ///////////////////////////idle state///////////////////////////////
begin
ns_rx=S0;
load_rx=1;
flag_rx=1;
end
end
S1:
begin
shift_register_rx[0]=rx;
ns_rx=S2;
load_rx=0;
flag_rx=0;
end

S2:
begin
shift_register_rx[1]=rx;
ns_rx=S3;
load_rx=0;
flag_rx=0;
end

S3:
begin
shift_register_rx[2]=rx;
ns_rx=S4;
load_rx=0;
flag_rx=0;
end

S4:
begin
shift_register_rx[3]=rx;
ns_rx=S5;
load_rx=0;
flag_rx=0;
end

S5:
begin
shift_register_rx[4]=rx;
ns_rx=S6;
load_rx=0;
flag_rx=0;
end

S6:
begin
shift_register_rx[5]=rx;
ns_rx=S7;
load_rx=0;
flag_rx=0;
end

S7:
begin
shift_register_rx[6]=rx;
ns_rx=S8;
load_rx=0;
flag_rx=0;
end

S8:
begin
shift_register_rx[7]=rx;
ns_rx=S9;
load_rx=0;
flag_rx=0;
end

S9:
begin
data_rx=shift_register_rx;
load_rx=1;
ns_rx=S0;
flag_rx=1;
end

default:
begin
ns_rx=S0;
flag_rx=1;
end
endcase
end
endmodule

 

 

TEST BENCH

 

 

`timescale 1ns/1ps
module uuart_tb;
reg clk;
reg rst;
reg load_tx;
reg [7:0] data_tx;
reg rx;
wire baud_gen;
wire flag_tx;
wire flag_rx;
wire tx;
wire [7:0] data_rx;
uuart_rtl ac(clk,rst,load_tx,data_tx,rx,baud_gen,flag_tx,flag_rx,tx,data_rx);

 

initial
begin
clk=0;
forever #41.667 clk=~clk;
end

 

initial
begin
rst=0;
repeat(5) @ (posedge clk);
rst=1;
repeat(5) @ (posedge clk);
rst=0;
repeat(500000) @ (posedge clk); $finish;
end

 

initial
begin

 

repeat(5)@ (posedge baud_gen);
load_tx=1;
data_tx=8'b10101010;
@(posedge baud_gen);
load_tx=0;
repeat(5) @(posedge baud_gen);
wait(flag_tx==1);

repeat(3)@ (posedge baud_gen);
load_tx=1;
data_tx=8'b10101110;
@(posedge baud_gen);
load_tx=0;
repeat(5) @(posedge baud_gen);
wait(flag_tx==1);
end

 

initial
begin
rx=1;
repeat(3) @(posedge baud_gen);
@ (posedge baud_gen);
rx=1'b0;
@ (posedge baud_gen);
rx=1'b1;
@ (posedge baud_gen);
rx=1'b0;
@ (posedge baud_gen);
rx=1'b1;
@ (posedge baud_gen);
rx=1'b0;
@ (posedge baud_gen);
rx=1'b1;
@ (posedge baud_gen);
rx=1'b0;
@ (posedge baud_gen);
rx=1'b1;
@ (posedge baud_gen);
rx=1'b0;
@ (posedge baud_gen);
rx=1'b1;



rx=1;
repeat(3) @(posedge baud_gen);
@ (posedge baud_gen);
rx=1'b0;
@ (posedge baud_gen);
rx=1'b1;
@ (posedge baud_gen);
rx=1'b0;
@ (posedge baud_gen);
rx=1'b1;
@ (posedge baud_gen);
rx=1'b0;
@ (posedge baud_gen);
rx=1'b1;
@ (posedge baud_gen);
rx=1'b0;
@ (posedge baud_gen);
rx=1'b1;
@ (posedge baud_gen);
rx=1'b0;
@ (posedge baud_gen);
rx=1'b1;
// repeat(5) @(posedge baud_gen);
//wait(flag_rx==1);
end

 

initial
$monitor("clk=%b,rst=%b,load_tx=%b,data_tx=%b,rx=%b,baud_gen=%b,flag_tx=%b,flag_rx=%b,tx=%b,data_rx=%b",clk,rst,load_tx,data_tx,rx,baud_gen,flag_tx,flag_rx,tx,data_rx);
endmodule

 

Waveform